1. Field of the Invention
The present invention relates in general to redundant line decoding in a semiconductor memory array and in particular to a redundant decoder master enable circuit. Still more particularly, the present invention relates to a redundant decoder master enable circuit which allows multiple enable signal inputs.
2. Description of the Prior Art
Modern VLSI semiconductor memories typically range in size from 64 Kb to 4 Mb. Processing defects in SRAM and DRAM semiconductor memories can significantly reduce the processing yield in such large scale memory arrays. In order to improve the processing yield of memory chips, various methods of error correction have been created to improve yield. These include electrical or `soft` error correcting whereby software corrects for physical defects, and `hard` error correcting whereby defective circuit elements are replaced with redundant elements included on the chip. The use of soft or hard error correcting can result in lower capital manufacturing cost and earlier introduction of new products on existing wafer fab lines or in new process technologies.
Yield enhancement by `hard` error correcting on a memory chip is typically produced by including redundant rows and columns within the memory array. A few redundant rows or columns can significantly enhance yield of a memory circuit since many devices are rejected for single bit failure or failures in a single row or column. These redundant rows or columns can be added to the memory design to replace defective rows or columns which are identified at electrical test after wafer processing. First, the defective row or column is disconnected from the array. This is accomplished by one of three methods: current blown fuses, laser blown fuses, and laser annealed resistor connections. Then a redundant row or column is enabled and programmed with the defective row or column address.
The implementation of redundant lines in a memory array can impair the chip's speed if these lines are a significant distance away from the lines they are replacing or if the circuit path for the redundant lines contains additional devices. The attempt is usually made to locate the redundant elements in blocks of the array near the locations they will replace in order to reduce the signal path length. Also, additional signals such as "chip enable" or "left/right row address" are needed to enable the line. These additional signals require an additional logic device to be placed in the signal path or that the fan-in on an existing logical device be increased. Both of these options introduce an additional delay in the signal path. This creates a mismatch between the signal path delay time through the redundant line and the non-redundant row or column. The result is a slower speed memory.
It would be desirable to provide a redundant line enable circuit which allows multiple enable signal inputs without introducing a propagation delay in the line select signal path. Such a circuit would allow for yield enhancement by `hard` error correction without resulting in a reduced memory chip speed.